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Silicon Labs /EFR32MG21B020F512IM32 /RAC_S /CLKMULTEN1

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Interpret as CLKMULTEN1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKMULTINNIBBLE 0 (disable)CLKMULTLDCNIB 0 (disable)CLKMULTLDFNIB 0 (disable)CLKMULTLDMNIB 0 (quarter_nibble)CLKMULTRDNIBBLE

CLKMULTRDNIBBLE=quarter_nibble, CLKMULTLDCNIB=disable, CLKMULTLDFNIB=disable, CLKMULTLDMNIB=disable

Fields

CLKMULTINNIBBLE

CLKMULTINNIBBLE
CLKMULTLDCNIB

CLKMULTLDCNIB

0 (disable): undefined

1 (enable): undefined
CLKMULTLDFNIB

CLKMULTLDFNIB

0 (disable): undefined

1 (enable): undefined
CLKMULTLDMNIB

CLKMULTLDMNIB

0 (disable): undefined

1 (enable): undefined
CLKMULTRDNIBBLE

CLKMULTRDNIBBLE

0 (quarter_nibble): undefined

1 (fine_nibble): undefined

2 (moderate_nibble): undefined

3 (coarse_nibble): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data